1. Field of the Invention
The present invention relates to a method for making a silicon-on-insulator (SOI) metal oxide silicon field effect transistor (MOSFET), and a method for making SOI MOSFETs capable of improving variations in threshold voltage and a parasitic bipolar effect generated in the formation of fully depleted (FD) SOI semiconductor integrated circuits using a recess channel.
2. Description of the Related Art
FD SOI MOSFET devices have superior characteristics such as an ideal subthreshold slope, perfect isolation, no parasitic capacitance and no floating body effect. However, in such FD SOI MOSFET devices, it is difficult to maintain desired threshold characteristics in the formation of channels. The difficulty is largely based on the insufficient thickness of an SOI film and a severe variation in the thickness of the SOI film. Another problem with these types of FD SOI MOSFET devices is an increase in resistance during the formation of source/drain regions due to the insufficient thickness of the SOI film.
In order to solve the problems associated with conventional FD SOI MOSFET devices, a method has been proposed which uses a recess channel. In accordance with this method, an oxide film is formed to a desired thickness following the formation of a structure consisting of an oxide film and a nitride film arranged at a region other than a channel. The oxide film is then removed. This method is known as a local oxidation of silicon (LOCOS) method. However, the LOCOS method involves the formation of bird""s beaks. When a gate is formed at a region where a bird""s beak is formed, a variation in the thickness of the oxide occurs. As a result, the layout of transistors is limited by their width and length.
Although the conventional method of making FD SOI MOSFETs using a recess channel provides an improvement in source/drain resistance, the thickness of the gate oxide film at the channel region may vary due to the presence of birds beaks.
In order to apply the conventional method of making FD SOI MOSFETs using a recess channel to the fabrication of ultra-micro devices, the method should be configured to adjust a variation in the thickness of a thin SOI film. In particular, the thickness of channel edge portions should be adjusted.
In the conventional FD SOl MOSFET making method, the ion implant conducted for the SOI film should be carried out at a very low ion energy in order to obtain a desired threshold voltage. This is because the SOI film is thin. Furthermore, a desired channel profile should be maintained during the ion implant because the ion implant may affect the produced FD SOI MOSFET.
FD SOI MOSFETs also do not have a lightly doped drain (LDD) region to accomplish high integration. When an FD SOI MOSFET is fabricated using a recess channel structure, it may have an LDD region with a limited width depending on the structure of the FD SOI MOSFET. The width is limited because the region, where a recess is to be formed, has a width corresponding to the sum of the channel width and two times a spacer width.
In the case of FD SOI MOSFETs having no LDD regions or a reduced LDD width, a parasitic bipolar effect may occur. For this reason, FD SOI MOSFET making methods using a recess channel should be configured to improve the parasitic bipolar effect. Therefore, in accordance with conventional FD SOI MOSFET making methods using a recess channel, germanium (Ge) ions are implanted in source/drain regions. Alternatively, argon (Ar) ions are implanted at a tilt angle of 45xc2x0 or more after the removal of spacers.
The ion implant conducted in the above mentioned conventional FD SOI MOSFET making methods using a recess channel is the easiest method capable of achieving an improvement in working voltage. However, germanium (Ge) ions should be implanted in source/drain regions in a high concentration of 10% or more. Otherwise, a tilt implant should be carried out at a sharp angle after removal of the spacers. For this reason, a degradation in reproducibility occurs. Furthermore, ions may be implanted even in a region not to be implanted with ions. Consequently, the device produced has a structure in which degradation in thermal carriers easily occurs.
Therefore, the present invention has been made in view of the above mentioned problems. A feature of the present invention is to provide an SOI MOSFET making method capable of improving a variation in threshold voltage and a parasitic bipolar effect generated in the formation of FD SOI semiconductor integrated circuits using a recess channel.
In accordance with one aspect, the present invention provides a method for making a silicon-on-insulator metal oxide silicon field effect transistor comprising the steps of: sequentially forming a buried oxide film and an active silicon film over a silicon-on-insulator substrate; forming a first photoresist film on the active silicon film; implanting ions in a portion of the active silicon film exposed after the formation of the first photoresist film, thereby forming a recess channel region; etching the active silicon film to a desired depth while using the first photoresist film as a mask, thereby forming a channel at the recess channel region; forming dummy spacers at opposite side walls of the etched active silicon film, respectively; forming a gate on the recess channel region between the dummy spacers; removing the first photoresist film, and forming a second photoresist film on a portion of the active silicon film exposed after the removal of the first photoresist film, and on the gate, except for regions where the dummy spacers are formed, respectively; implanting ions in portions of the recess channel region each defined between the gate and an associated one of the dummy spacers, thereby forming lightly doped drain regions, respectively; removing the dummy spacers, and implanting low-concentration impurity ions in portions of the recess channel region defined at opposite sides of the gate, thereby forming lightly doped ion regions, respectively; forming spacers at opposite side walls of the recess channel region, respectively; removing the second photoresist film, and implanting high-concentration impurity ions in the active silicon film, thereby forming a source region and a drain region; and forming source/drain electrodes and a gate electrode on a structure obtained after the formation of the source and drain regions, in accordance with a metal line process.
The method further comprises the step of forming a suicide film on the source and drain regions.
In accordance with another aspect, the present invention provides a method for making a silicon-on-insulator metal oxide silicon field effect transistor comprising the steps of: sequentially forming a buried oxide film and an active silicon film over a silicon-on-insulator substrate; forming a first photoresist film on the active silicon film; implanting ions in a portion of the active silicon film exposed after the formation of the first photoresist film, thereby forming a recess channel region; etching the active silicon film to a desired depth while using the first photoresist film as a mask, thereby forming a channel at the recess channel region; forming dummy spacers at opposite side walls of the etched active silicon film, respectively; forming a gate on the recess channel region between the dummy spacers; removing the first photoresist film, and forming a second photoresist film on a portion of the active silicon film exposed after the removal of the first photoresist film, and on the gate, except for regions where the dummy spacers are formed, respectively; implanting ions in portions of the recess channel region each defined between the gate and an associated one of the dummy spacers, thereby forming lightly doped drain regions, respectively, while implanting low-concentration impurity ions in portions of the recess channel region defined at opposite sides of the gate, thereby forming lightly doped ion regions, respectively; forming spacers on the dummy spacers, respectively; removing the second photoresist film, and implanting high-concentration impurity ions in the active silicon film, thereby forming a source region and a drain region; and forming source/drain electrodes and a gate electrode on a structure obtained after the formation of the source and drain regions, in accordance with a metal line process.